Semiconductor chip manufactures and packagers sometimes use ball grid arrays ("BGAs") to interconnect semiconductor chips to external circuits such as printed circuit boards. Using BGA technology, a semiconductor chip is connected to a printed circuit board using solder connections. When solder alone is used to interconnect the contacts on the semiconductor chip to the printed circuit board, the solder columns are typically short in order to maintain the structural integrity of the solder column. As a result, the solder columns have minimal elastic properties and are susceptible to solder cracking due to mechanical stress that result from differences in the coefficients of thermal expansion ("CTE") of the chip and the printed circuit board. When the chip heats up during use, both the chip and printed circuit board expand but at different rates and by different amounts. The chip and the board tend to cool down when the chip is not in operation. As the chip and the board cool, both tend to contract but at different rates and by different amounts. This time-wise and amount-wise variation in expansion and contraction stresses the interconnections between the chip and the printed circuit board.
Several inventions commonly assigned to the assignee of the present invention deal effectively, but differently, with this thermal cycling problem. Such inventions include U.S. Pat. Nos. 5,148,265; 5,148,266; 5,477,611; 5,548,091; 5,663,106; and 5,659,952; and U.S. patent applications with Ser. No. 08/987,720 (filed on Jun. 20, 1997); Ser. No. 08/842,313 (filed on Apr. 24, 1997); and Ser. No. 08/931,680 (filed on Sep. 16, 1997). The specifications of all of the above listed patent and patent applications are incorporated by reference herein. Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.